参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 84/92页
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
85
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix E—BSM2 Operation as a Function of Phase Relation of TCK and TCKIN
at High Speeds with Low-Valued Clock Divider
When operating the BSM2 at high speeds, careful consideration must be given to the clock phases, in particular,
the phase relationship of TCKIN to TCK and the relationship of the TAP signals, TMS, TDO and TDI. To illustrate
potential problems, some examples are shown in the following figures.
Case 1: Consider the situation with TCK = TCKIN/1 and with TCKIN operating at 6.5 MHz (fmax/10—with a period
of 152 ns). For this divide by 1 application, TCK is equal to the inverted TCKIN plus a delay of approxi-
mately 11 ns. At 6.5 MHz, this delay has negligible consequence as shown in Figure 18. TMS and TDO
change state based on the positive edge of TCKIN which in the case of divide by 1 is the negative edge of
TCK—this meets the
IEEE Std. 1149.1 specification. In this application, TDI is captured on the positive
edge of TCKIN—matching the best margin for TDI capture for this device. (The
IEEE specification
requires capture on the positive edge of TCK which is the negative edge of TCKIN. This requirement is
met in this example, because of the black box argument—the behavior of the B-S chain and the values
scanned in and out of it cannot be distinguished from a part operating precisely as specified by the Stan-
dard without knowledge of the internal workings of the BSM2.) Since the negative edge of the signal on
TCK is where the signal on TDI can make a transition and this lags the rising edge of the signal on TCKIN,
latching TDI on the positive edge of TCKIN may be late; but it’s safe—it preserves proper operation. Typi-
cal propagation delays from TCKIN to TMS, TDO and TCK are 15 ns, which is approximately 10% of the
period.
The dashed box (A) represents the capture range of TDI with respect to the appropriate clock edge of
TCKIN in all of the figures.
Figure 18. Relationships of TCKIN, TCK, TDI, TDO, and TMS with TCKIN Frequency of 6.5 ns and TMS
Defined by Clock Divider Value of 1
TDI is sampled wrt TCKIN
(set up 10 ns, hold 5 ns)
TCKIN
TCK
TMS,TDO
TDI
Out Data
N
Out Data
N + 1
Out Data
N + 2
In Data
N
In Data
N + 1
In Data
N + 2
Phase
N
Phase
N
A
11 ns delay
BSM2 samples TDI here.
TDI is liable to change state here.
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