参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 71/92页
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
73
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix C—BSM2 (497AE) Data Sheet (continued)
Read/Write Cycle Timing—Synchronous Operation (continued)
5-6324 (F)
Notes:
1. DAV* is deasserted. But CE* is still asserted so BSM2 maintains valid data on the data bus.
2. D[7:0] output buffers are disabled asynchronously after CE* goes to logic 1.
3. CE* is deasserted, but DAV* is still asserted. The write cycle is terminated by either CE* going inactive or DAV* going inactive. At that point,
the write cycle is terminated.
Figure 12. 497AE Cycle with CE* and DAV* Deasserted Separately
The length of a BSM2 internal register ranges from 8 bits to 32 bits. Although the preceding timing diagrams are
valid for all modes of read/write operations, it is useful to keep the following points in mind while accessing any of
the BSM2 internal registers:
To write data into an m-byte register, a total of m consecutive write operations must be performed starting with the
least significant byte. Reading the register before m write operations have been completed may produce undesir-
able effects. Similarly, to read an m-byte register, a total of m consecutive read operations must be performed start-
ing with the least significant byte. Writing the register before m read operations have been completed may produce
undesirable effects.
TCKIN
CE*
RA
R/W*
DAV*
D[7:0]
READ CYCLE
WRITE CYCLE
1
2
3
WAIT
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