参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 58/92页
文件大小: 1041K
代理商: 1215E
Agere Systems Inc.
61
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
NCR: Net Count Register
Purpose
Provides capability for the controlling processor to program the number of B-S accessible nets driven/sensed by
the selected/attached B-S chain; is used by the ATPG for generating interconnect test patterns.
Address (Octal)
22
Format
Default (Hex)
NCR = 0000
Read-only Bits
None
Description
This 16-bit register is used by the ATPG function of the BSM2 in conjunction with the net counter (NC) for generat-
ing counting and walking sequences. Typically, the NCR is loaded with the number of B-S accessible nets driving
(driven by) the selected/attached B-S chain. When a counting or walking sequence is to be generated, the contents
of the NCR are loaded into the NC when the BSM2 enters the execution mode. Then, the NC is decremented by
one for every bit of the algorithmic test vector that is shifted out to an active B-S output cell (i.e., whenever the
serial output of the TVI Test Data Memory (FIFO) is low). Otherwise, the counter is inhibited. Note that there are as
many active B-S output cells as there are B-S accessible nets. After the NC has reached zero, it is reloaded with
the contents of the NCR before counting down again. This process is repeated until a specified number (contained
in the loop counter, LPC) of algorithmic patterns has been delivered to the B-S ring.
15—00
NCR[15:00]
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