参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 57/92页
文件大小: 1041K
代理商: 1215E
60
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
SDR: Scan Duration Register
Purpose
Provides the means by which the controlling processor can program the number of bits in, or the length of, a serial
test pattern to be generated during ATPG operation. See Automatic Test Pattern Generation (ATPG), Scan
Sequence Modification (SSM), and Signature Analysis.)
Addresses (Octal)
21
Format
Default (Hex)
SDR = 0000
Read-only Bits
None
Description
This 16-bit register is to be loaded with the number of serial test data bits to be shifted out to the selected/attached
B-S chain via TDO during ATPG operation. Typically, the number equals the length of the B-S ring. The contents of
the SDR are loaded into the scan duration counter (SDC) prior to shifting each newly generated serial test vector
(see under the heading BSM2 Registers Related to ATPG). The SDC is decremented by one in each TCK cycle
beginning as soon as the TAP Controller(s) targeted by the BSM2 has (have) entered a Shift-DR controller state
during ATPG execution. When SDC reaches zero, the shifting process of a single serial vector has been com-
pleted.
15—00
SDR[15:00]
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