参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 68/92页
文件大小: 1041K
代理商: 1215E
70
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix C—BSM2 (497AE) Data Sheet (continued)
Read/Write Cycle Timing—Synchronous Operation (continued)
A write cycle begins when the BSM2 is enabled and R/W* = 0 (see Figure 8). The D[7:0] output buffers are dis-
abled during a write cycle. Also, the input data on the D[7:0] data bus are internally latched on the first rising edge
of TCKIN after DAV* goes to logic 0. The write cycle terminates when the BSM2 has detected a logic 1 at DAV* on
a subsequent TCKIN rising edge. This implies that every write cycle consumes at least two TCKIN cycles.
D[7:0] output buffers are controlled asynchronously by CE* and R/W*. When a BSM2 register is to be written after
a series of read operations, D[7:0] change from outputs to inputs; this takes a maximum of 15 ns (see Figure 11).
5-6320 (F)
Notes:
1. DAV* going to logic 0 while CE* and R/W* are held = 0 signifies the start of a write cycle; the BSM2 latches the input data D[7:0] on the rising
edge of TCKIN.
2. DAV* = 1 on the rising edge of TCKIN causes the BSM2 to terminate the write cycle.
3. No further write operations will occur (i.e., no additional data will be written into the BSM2) while DAV* is still = 0.
4. Successive write cycles must be terminated/delimited by a logic-1 value of R/W* which lasts for at least one TCKIN cycle.
Figure 8. 497AE Write Cycle Timing Diagram
SHORT CYCLE
EXTENDED CYCLE
TCKIN
CE*
RA
R/W*
D[7:0]
DAV*
12
1332
4
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