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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 64/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
67
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix C—BSM2 (497AE) Data Sheet (continued)
Pin Descriptions (continued)
Table 6. 497AE Processor Interface Pins
The following pins are used to provide the parallel interface between the BSM2 and a generic processor or an ATE.
Pin
Symbol
Name/Description
1CE*
Chip Enable (Active-Low). This input pin is active-low. When CE* = 0, the BSM2 is
enabled or selected. The BSM2 data bus D[7:0] becomes active, and the BSM2 internal
registers can be accessed by the controlling processor.
2R/W*
Read/Write Control (Active-Low). When the BSM2 is enabled (CE* = 0), this input pin
controls the direction of data transfer. When R/W* = 1, D[7:0] become outputs, indicating a
BSM2 internal register is to be read. When R/W* = 0, D[7:0] become inputs, indicating a
BSM2 internal register is to be written.
3RA
Register Address. When the BSM2 is enabled, this input pin is used to select a BSM2
internal register. When RA = 0, the pointer register (PTR) is addressed; when RA = 1, the
internal register, whose address is in the pointer field of the PTR, is selected (see under
the heading 497AE Addressing (Indirect) on page 36).
4DAV*
Data Available/Valid (Active-Low). This active-low input pin indicates when the data
placed on the data bus is valid and ready to be strobed. DAV* is operational only in the
synchronous interface mode; and the value on the DAV* input has an effect on the BSM2
only when the BSM2 is enabled (CE* = 0).
6TCKIN
Test Clock Input. This is a 50% duty cycle clock input with a maximum frequency of
65 MHz. The TCK clock output is derived from this input clock. All internal BSM2 opera-
tions are synchronous with respect to TCKIN.
9RST*
Reset (Active-Low). This active-low input pin can be used to synchronously reset the
entire device. A low pulse applied to RST* on the rising edge of the signal on TCKIN is suf-
ficient to initiate the BSM2 internal reset operation. All of the output and bidirectional sig-
nals are set to a high-impedance state when RST* = 0.
11
SYNC_HIF* Synchronous Host Interface (Active-Low). This pin defines host interface operation. If
SYNC_HIF* = 0, then the interface will operate synchronously as in 497AA mode. If
SYNC_HIF* = 1 or if the pin is left unconnected, the interface will operate asynchronously
(Figure 15 and Figure 16). There is an internal pull-up on this pin. This pin should not be
switched during operation of the BSM2.
13
INT*
Interrupt (Active-Low). This is an active-low, open drain (open collector) output pin. It
generates processor interrupts (e.g., for FIFO over-/underflow or completion of BIST).
(See discussion under Interrupt Control.) For proper operation, this pin should be termi-
nated with a pull-up resistor.
16
RDY
Ready. This pin is only used in asynchronous operation of the host interface. This output
pin provides the handshake signal to the controlling processor. The pin has no function
when the device is operating in 497AA Compatibility Mode.
18
BSM_MD*
BSM Mode (Active-Low). This pin defines the operational mode of the device. It should
be tied to logic 0 for operation in 497AA Compatibility Mode. If tied to logic 1 or left uncon-
nected, an internal pull-up will cause the device to operate in Advanced Operational mode.
This pin should not be switched during operation of the BSM2.
28—25,
23—20
D[7:0]
Data Bus. These eight pins are bidirectional, with D0 being the least significant bit (LSB)
and D7 the most significant bit (MSB). The data bus is active if the device is enabled, and
the direction of the data bus (input or output) is controlled by the R/W* pin. The controlling
processor accesses the BSM2 internal registers through these pins.
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