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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 29/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
35
User Manual
April 2001
497AE and 1215E Boundary-Scan Master 2
Advanced Operational Mode
Appendix B—BSM2 Internal Register
Descriptions
General Introduction and Conventions
The BSM2 contains a number of 16-bit and 32-bit reg-
isters through which it is programmed and from which
results and status of BSM2 operation can be read. The
means of addressing these registers (indirectly and
directly) and the details of reading and writing these
registers are detailed under the heading BSM2 Regis-
ter Addressing, Reading, and Writing.
In each of the subsections of the present appendix, the
functionality of a BSM2 internal register (BIR) is
described in detail. The main purpose and the format
(bit assignments) of each BIR is also given. The
address of each 16-bit word of each BIR is provided in
octal notation.
Note:
There is no register defined with addresses 23
and 30—40 (octal).
The default values of the registers (if any) are speci-
fied. These values correspond to the initial states of the
registers immediately upon device reset or powerup,
and they are presented in hexadecimal notation unless
indicated otherwise.
The following conventions are used in this section:
s
BIR[
a] refers to the BSM2 register with the octal
address value
a. This applies in both the cases of
direct and indirect register addressing.
s
SIG_NAME, BIR[
a, b] indicates that the signal
SIG_NAME resides in the
bth bit of the BIR with
address
a. In this case, b is a decimal integer and a
is octal.
s
In graphical presentations of registers, the most sig-
nificant bit is presented on the left.
Note:
In the following register descriptions only those
bits that are read-only bits will be indicated. All
by the controlling processor.
Note:
The CMU (Control-MASK/USEROUT0(1)regis-
ter—involved in control of internal connection
of BSM2 register bits to the user I/O pins of the
BSM2) is active only in the 48-pin package—
the 1215E.
Throughout this section, an X denotes a “don’t care” bit
or an undefined state. The register address space is
incompletely specified so as to allow for possible future
increases in the number of BIRs.
Unused Addresses
There are ten unused addresses—23 and 30—40
(octal). Writing to an illegal address will have no effect
on the contents of any BIR. Reading from an illegal
address will result in undefined data, and will have no
effect on the contents of any BIR.
Classification of Registers
When learning the use of the BIRs, it may be helpful to
remember that BIRs are of two types:
s
Registers used in the programming of scanning
tasks (writing to these registers does not cause an
immediate effect)
s
Registers that are not associated directly with a
scanning task, but facilitate altering the configuration
of the BSM2 (writing to these registers causes an
immediate effect described in the relevant register
descriptions, below).
In the 497AE, register addressing is managed through
a register (PTR) that is not a BIR.
BSM2 Register Addressing, Reading,
and Writing
All registers are readable in the Advanced Operational
Mode.
Data Bus Widths
The 1-bit data bus width supported in the 497AA is
not
supported in the 1215E and is not supported in the
497AE in Advanced Operational Mode. The data bus is
8 bits wide in the 497AE (see Appendix C—BSM2
(497AE) Data Sheet) and 16 bits wide in the 1215E
(see Appendix D—BSM2 (1215E) Data Sheet).
Address Bus Width
The 497AE external address bus comprises 1 bit. This
entails indirect addressing of internal registers (see
below). The 1215E external address bus is 5 bits wide
allowing direct addressing of internal registers.
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