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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 30/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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36
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Internal Register
Descriptions (continued)
BSM2 Register Addressing, Reading, and
Writing (continued)
497AE Addressing (Indirect)
Addressing in the 497AE is accomplished in two steps.
First the PTR register must be selected by driving the
RA pin of the 497AE to 0. The first subsequent write to
the 8-bit data bus (D[0:7]) will be taken to be the
address of the BIR to be accessed. Only the 5 low
order bits of the byte written will be decoded as a BIR
address.
497AE Register Size, Byte Transfer, and Synchroni-
zation of Reads and Writes
The 8-bit data bus of the 497AE can accommodate
only single-byte read and write operations. A BIR can
have a length of 2 or 4 bytes. As a result, access to an
n-byte BIR normally takes exactly n consecutive single-
byte bus cycles to complete. The order of transfer is
from the lowest-order byte to the highest-order byte.
To enable the controlling processor to synchronize
multibyte data transfers, all BIRs are designed such
that whenever the processor writes into the PTR, the
lowest-order byte of the selected BIR will always be the
first byte to be transferred in a subsequent BIR read or
write operation—regardless of any prior byte transfers.
So if, in error, a user’s microcode transfers 3 bytes to a
4-byte register, writing the PTR will always produce
resynchronization and ensure that the next read or
write will start with the lowest-order byte of the next
register target.
Even though the user may be confident that resynchro-
nization is easily achieved, it may be necessary to
know the results when insufficient bytes have been
transferred to achieve the full writing of some register.
Assume that m < n. Then, the effect of an m-byte trans-
fer to or from an n-byte BIR (occurring between any
two consecutive PTR writes) varies according to the
following conditions:
s
If the BIR is either TVOR or TVIR, then the contents
the address pointer (APO or API) will be unchanged
by the incomplete write. All TVOR and TVIR data
transfers must occur in multiples of 16-bit words.
s
Otherwise, the least significant m bytes of the BIR
will have been written if the transfer was a write oper-
ation. The higher n-m bytes of the BIR will have
retained the values they held prior to the incomplete
write operation. In other words, with 8-bit bus size
selected, all BIR write operations are byte-effective—
they alter contents of a BIR along the byte bound-
aries.
A memory buffer (FIFO) example: to write into the 2-
byte TVOR, a total of two single-byte write cycles are
required, starting with the first byte (byte 0). The entire
word in the TVOR is written into the TVO memory only
after the second byte (byte 1) has been written into the
TVOR. If, for some reason, the processor selected
another BIR (through a PTR write) just after the trans-
fer of the first byte (byte 0), then data transfer would
restart with the first byte (byte 0) of the newly selected
BIR (byte transfer is thus resynchronized). Moreover,
the contents of the TVOR (partially altered) would not
have been written into the TVO.
A nonmemory buffer (FIFO) example: had the BIR in
question been SAR instead of TVOR, the first byte
would have been written into the lowest-ordered byte
(byte 0) of the SAR. The remaining 3 bytes of the SAR
(byte 1—byte 3) would have retained the values they
held prior to the incomplete write operation.
1215E Addressing (Direct)
The address of the register to be read or written is writ-
ten to the 5-bit address bus (RA[0:4]). The address is
directly decoded; and the addressed BIR, selected.
1215E Data Reads and Writes
In the 1215E, a 32-bit register is accessed via two
sequential address operations on the RA[0:4] bus.
Data transfer occurs on 16-bit word boundaries by
reading to, or writing from, the 16-bit data bus
(D[0:15]). The 1215E differs from the 497AE in that the
latter latches an address and automatically indexes it
as a read or write requires.
Timing of events associated with reading and writing
specific registers is addressed in the following section.
Timing of Actions Resulting from Writing
Registers
Actions Taken Upon Writing a Register (497AE
Synchronous Operation)
An action programmed by means of writing to a BIR
occurs on the second
positive edge of TCKIN after CE*
goes active (is driven to 0) following latching of the
input data. See Figure 8 and Figure 16.
Actions Taken Upon Writing a Register (Asynchro-
nous Operation—497AE and 1215E)
An action programmed by means of writing to a BIR
occurs on the second
positive clock edge after CE*
goes inactive (is driven to 1).
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