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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 78/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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8
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Architecture of the BSM2 (continued)
Test Data Memories (FIFOs)
There are two test data memories (TVI and TVO).
Each consists of 8K bits organized in 512 16-bit words.
They behave as FIFOs during normal load-scan-
unload operation. In such a case, it is not necessary for
the controlling processor to specify addresses for writ-
ing to, or reading from, the test data memories. To
reset a FIFO, the relevant address pointer register (API
or APO) can be loaded with the value 0.
However, in ATPG mode the test data memories do not
operate as FIFOs. In such a case, these memories
hold information about circuit interconnect necessary to
create conflict-free ATPG. FIFO organization is not
appropriate in ATPG mode. In this mode, BSM2 needs
a memory pointer permitting it to loop through the cir-
cuit interconnection information—once for each vector
to be generated. In ATPG mode, the words of the
memories can be written and read individually using
their respective address pointer registers, API and
Analysis.)
TVI Test Data Memory (FIFO)
This 8K-bit memory receives the output test data from
the selected/attached B-S chain during normal scan
operation.
During ATPG operation, the B-S chain output data
stream is re-directed to a signature analysis register
(SAR). The TVI test data memory is used during ATPG
for a portion of a circuit map that permits the test gen-
eration function to avoid bus conflict in the application
of otherwise circuit independent algorithms. More
Modification (SSM), and Signature Analysis.
TVO Test Data Memory (FIFO)
This 8K-bit memory stores the test stimulus data to be
scanned into a selected/attached B-S chain during nor-
mal scan operation.
During ATPG operation, the test stimulus is provided
by the test pattern generation hardware. The TVO test
data memory is used to store a portion of the circuit
map mentioned above.
User-Definable I/O (1215E Only)
The 1215E provides three pins for user-definable I/O—
USERIN, USEROUT1, and USEROUT2. These might
be interfaced to a DMA controller, for example.
USERIN
The USERIN pin provides the capability of optionally
monitoring the state of a user selected signal without
adding additional parallel I/O decoding logic to a
design. Because of pin limitations it is not available on
the 497AE device. If it is unused in the 1215E design, it
should not be left floating, but tied either high or low.
Note: The USERIN signal is not latched in the BSM2.
Stability of this signal is the responsibility of the
user.
USEROUT0
The USEROUT0 pin provides the means of signalling
an interrupt to the controlling processor according to
certain conditions of the Test Data Memories (FIFOs)
(e.g., full, empty, etc.).
The pin can be considered to be the output of a 9-input
OR tree as follows: The USR0 bit in the CUTO register
is ORed with the STAT[15:12] and STAT [3:0] bits of the
status register under control of a mask programmed in
the USRC0[7:0] bits of the CMU register.
USEROUT1
The USEROUT1 pin provides the means of signalling
an interrupt to the controlling processor according to
certain conditions of the Test Data Memories (FIFOs)
(e.g., full, empty, etc.).
The pin can be considered to be the output of a 9-input
OR tree as follows: The USR1 bit in the CUTI register
is ORed with the STAT[15:12] and STAT [3:0] bits of the
status register under control of a mask programmed in
the USRC1[7:0] bits of the CMU register.
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