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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 67/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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Agere Systems Inc.
7
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Architecture of the BSM2
TAP, Power, and Ground Pins
Both the 497AE (Table 7) and 1215E (Table 18) have a
5-pin TAP interface. Details of power and ground pinout
can be found in Table 8 (497AE) and Table 19 (1215E).
BSM_MD* (497AE only)
This pin defines the operational mode of the device. It
should be tied low for operation in 497AA compatible
mode. If tied high or left unconnected, an internal pull-
up will cause the device to operate in Advanced Opera-
tional mode. This pin should not be switched during
operation of the BSM2.
SYNC_HIF*
This pin defines host interface operation. If SYNC_HIF*
= 0, then the interface will operate synchronously as in
497AA mode. If SYNC_HIF* = 1 or if the pin is left
unconnected, the interface will operate asynchronously
(Figure 15 and Figure 16). There is an internal pull-up
on this pin. This pin should not be switched during
operation of the BSM2.
Processor Interface
The processor interface provides generic functionality
including chip enable (CE*), read/write control (R/W*),
data available/valid (DAV*), master clock input
(TCKIN), interface ready handshake control (RDY), and
interrupt signalling (INT*). The asterisk following a pin
name indicates that the signal on that pin is active low.
Basic functional description of the pinout of the 497AE
processor interface can be found in Table 6.
Basic functional description of the pinout of the 1215E
processor interface can be found in Table 17.
497AE Data Bus
The data bus (D[7:0]) of the 497AE is 8 bits wide per-
mitting writing and reading of BSM2 Internal Registers
(BIRs) on a byte-at-a-time basis. Details of read/write
ing 497AE Register Size, Byte Transfer, and Synchroni-
zation of Reads and Writes.
1215E Data Bus
The data bus (D[15:0]) of the 1215E is 16 bits wide
permitting writing and reading of the BIRs on a word-
at-a-time basis. Details of read/write operation are pro-
vided in Appendix B under the heading 1215E Data
Reads and Writes.
497AE Addressing
The 497AE preserves the indirect addressing opera-
tion of the 497AA. The RA pin is used to address a
Pointer Register (PTR). Once the PTR is selected, the
register address of a BIR to be accessed is placed in
the PTR by writing to the 497AE data bus. Details of
this indirect addressing are provided in Appendix B
under the heading 497AE Register Size, Byte Transfer,
One difference between the 497AA Compatibility Mode
and the Advanced Operational Mode of the 497AE is
that the device is
not reset by reading from PTR in
Advanced Operational Mode.
1215E Address Bus
The 1215E provides only a direct addressing method.
The address bus comprises the pins RA[4:0]. Further
information concerning use of the address bus is pro-
vided in Appendix B under the heading 1215E
Device Controller
The device controller provides coordination and syn-
chronization of the various modules depending on the
selected modes of operation. All registers and memory
states are selected: Execute, Jump, or Reset. In the
default mode, the TCK is free running, but can be set
to a gated mode such that the clock is off when the
device is in the nonexecuting mode.
In addition, the controller coordinates the internal self-
test operations of the BSM2 (see under the heading
BIST—Self-Test of the BSM2).
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