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| 型号： | 1215E |
| 英文描述： | TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC |
| 中文描述： | 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料 |
| 文件页数： | 65/92页 |
| 文件大小： | 1041K |
| 代理商： | 1215E |
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68
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix C—BSM2 (497AE) Data Sheet (continued)
Pin Descriptions (continued)
Table 7. 497AE Board-Level TAP Interface Pins
Notes:
The BSM2 interfaces with the board-level B-S ring, of which the BSM2 is master, through these five pins.
Careful timing and skew analysis of the signals on TDI, TDO, and TMS are required when operating with a clock divider of 1 or 2 at high fre-
quencies (see Appendix E—BSM2 Operation as a Function of Phase Relation of TCK and TCKIN at High Speeds with Low-Valued Clock
Table 8. 497AE Power and Ground Pins
5 V Tolerant Buffers
All I/Os are 5 V tolerant. For the input signals, they can be driven with standard TTL logic. The output and bidirec-
tional signals will drive only to a 3 V level (>high-level threshold TTL input voltage). When used in bused applica-
tions, the outputs and bidirectional signals can be driven to 5 V when in the high impedance state.
If the 3 V power supply fails during normal operations, no current will be drawn from pins supplying 5 V. However,
to minimize long-term degradation, these conditions should not last for long periods of time.
Pin
Symbol
Name/Description
8TDI
Test Data Input. This is a standard TAP serial test data input pin with an internal
pull-up resistor. It receives serial test response from the local board B-S ring. All
values arriving at TDI are latched on the rising edge of TCKIN defined with respect
to TCK. The test response can be stored in an on-chip memory buffer or com-
pressed into a 32-bit signature.
10
TRST*
Test Reset (Active-Low). This output is a standard TAP test reset signal. When
TRST* = 0, the TAP controllers in any selected/attached B-S chain are asynchro-
nously placed in their Test-Logic-Reset TAP Controller state.
12
TCK
Test Clock. This is a 50% duty cycle, standard TAP test clock output pin. This pro-
grammable clock output is derived from the TCKIN clock input. It is broadcast to
all the B-S devices supported by the BSM2. Its maximum frequency is 65 MHz.
Upon device reset, the default speed of the signal on TCK is 1/128 of the speed of
TCKIN.
14
TDO
Test Data Output. This is a 3-state, standard TAP serial test data output pin
which drives the local board B-S ring. All changes at TDO occur on the falling
edge of TCK, referenced by TCKIN. This pin can deliver prestored, deterministic
test vectors, or algorithmic patterns generated by the ATPG (see Appendix A).
17
TMS
Test Mode Select. All changes at TMS occur on the falling edge of TCK, refer-
enced by TCKIN. Upon device reset, this pin outputs a constant value of 1.
Pin
Symbol
Name/Description
5, 19
PWR/VDD Power Supply. Two 3 Vdc power input pins are used to minimize potential noise
in the power supply.
7, 15, 24
GND/VSS
Ground. Three ground pins (all at 0 Vdc) are used to minimize potential ground
bounces caused by high frequency and, potentially, high fanout pins such as TCK.
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