参数资料
型号: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 测试/ JTAG支持|的CMOS | QFP封装| 48PIN |塑料
文件页数: 32/92页
文件大小: 1041K
代理商: 1215E
38
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
CSC: Control-Scan/Clock Register
Purpose
Provides processor access to and control of various parameters of the scan operation of the BSM2 and of the low
power mode of the BSM2.
Address (Octal)
00
Format
Default (Hex)
CSC = 0000
Read-only Bits
None
Description
GCLK
(Gated Clock Bit)—A 0 in this bit causes the BSM2 to bring the TAPs of devices on the selected/
attached B-S chain into the Pause-IR or Pause-DR TAP Controller state automatically when the 8K bit
input (output) buffers experience overflow (underflow) during an instruction or data register scanning
sequence. A 1 in this bit causes the BSM2 to halt operation of the TAP Controllers of devices on the
currently selected/attached B-S chain by fixing the state of (gating) the TCK signal feeding the B-S
chain.
IDT[1:0]
(Idle Type Bits)—These two bits encode the name of a TAP Controller state. The values of the two
bits only have effect when the IDLE counter is nonzero. During a scan operation, if the IDLE counter
is nonzero, the first time the TAP Controller state designated by IDT[1:0] is reached (as monitored by
the state of the TAPS bits of the status (STAT) register), the IDLE counter will be activated and begin
downcounting. The BSM2 will hold the TAP Controller states of all devices on the selected/attached
B-S chain in the designated state until the IDLE counter contains 0. Then the scan operation pro-
grammed into the BSM2 will continue. If a scan operation is defined involving a sequence of TAP
Controller states that does not include the then defined Idle TAP Controller state, there will be no
effect from the setting of IDT[1:0].
Note:
For ATPG operation, the IDLE counter register should be set to zero, disabling the IDT bits.
15
14—13
12—10
09—08
07—04
01
02—00
GCLK IDT[1:0] SCT[2:0] DET[1:0] RTD[2:0] LP CDIV[2:0]
Designated Idle TAP Controller State
IDT1
IDT0
Test-Logic-Reset
0
Run-Test/Idle
0
1
Pause-IR
1
0
Pause-DR
1
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