参数资料
型号: XR18W750IL48-F
厂商: Exar Corporation
文件页数: 32/44页
文件大小: 0K
描述: IC WIRELESS UART CTRLR 48QFN
标准包装: 260
功能: 控制器
RF 型: 通用
次要属性: I²C 接口
封装/外壳: 48-VFQFN 裸露焊盘
包装: 托盘
其它名称: 1016-1473
XR18W750IL48-F-ND
XR18W750
WIRELESS UART CONTROLLER
FCTR[3:2]: Reserved
For normal operation, these bits should be ’0’.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 10 for more details.
T ABLE 14: T RIGGER T ABLE S ELECT
REV. 1.0.0
FCTR
B IT -5
0
0
1
1
FCTR
B IT -4
0
1
0
1
T ABLE
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
FCTR[6]: Scratchpad Swap
? Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
? Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.
? Logic 0 = Registers TRG and FC selected for RX.
? Logic 1 = Registers TRG and FC selected for TX.
5.19
Enhanced Feature Register (EFR)
EFR[3:0]: Reserved
For normal operation, these bits should be ’0’.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 (MCR
bits 7-5 should remain at their default values of ’0’). After modifying any enhanced bits, EFR bit-4 can be set to
a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the
enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
? Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
? Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Reserved
For normal operation, this bit should be ’0’.
32
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