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参数资料
| 型号： | XR18W750IL48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 14/44页 |
| 文件大小： | 0K |
| 描述： | IC WIRELESS UART CTRLR 48QFN |
| 标准包装： | 260 |
| 功能： | 控制器 |
| RF 型： | 通用 |
| 次要属性： | I²C 接口 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
| 其它名称： | 1016-1473 XR18W750IL48-F-ND |
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XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
3.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
3.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
F IGURE 7. R ECEIVER O PERATION IN NON -FIFO M ODE
16X C lock
R eceive D ata Shift
D ata Bit
R egister (R SR)
Validation
R eceive D ata C haracters
R eceive
D ata Byte
and Errors
Error
Tags in
LSR bits
4:2
R eceive D ata
H olding Register
(RH R)
R H R Interrupt (ISR bit-2)
R XFIFO 1
14
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相关代理商/技术参数 |
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|---|---|
| XR18W750IL48TR-F | 功能描述:UART 接口集成电路 XR18W750IL48TR-F RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR18W753 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER |
| XR18W753IL48 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER |
| XR18W753IL48-F | 功能描述:射频接收器 UART RoHS:否 制造商:Skyworks Solutions, Inc. 类型:GPS Receiver 封装 / 箱体:QFN-24 工作频率:4.092 MHz 工作电源电压:3.3 V 封装:Reel |
| XR18W753L48-0A-EB | 功能描述:界面开发工具 900MHz RF EVAL Board RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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