参数资料
型号: XR18W750IL48-F
厂商: Exar Corporation
文件页数: 31/44页
文件大小: 0K
描述: IC WIRELESS UART CTRLR 48QFN
标准包装: 260
功能: 控制器
RF 型: 通用
次要属性: I²C 接口
封装/外壳: 48-VFQFN 裸露焊盘
包装: 托盘
其它名称: 1016-1473
XR18W750IL48-F-ND
XR18W750
REV. 1.0.0
WIRELESS UART CONTROLLER
EMSR[6]: LSR Interrupt Mode
? Logic 0 = LSR Interrupt Delayed (for 16C550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
? Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Reserved
For normal operation, this bit should be ’1’.
5.12
FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12 for details.
5.13
Baud Rate Generator Registers (DLL and DLM) - Read/Write
These registers make-up the value of the baud rate divisor.
5.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x0A). Prior to reading this register, DLL and DLM should be set to 0x00.
5.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
5.16
Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register. If both the TX and RX trigger levels are used,
the TX trigger levels must be set before the RX trigger levels .
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
5.17
RX/TX FIFO Level Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See Table 12 .
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data.
5.18
Feature Control Register (FCTR) - Read/Write
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See Table 13 for more details.
31
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