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参数资料
| 型号： | XR18W750IL48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 27/44页 |
| 文件大小： | 0K |
| 描述： | IC WIRELESS UART CTRLR 48QFN |
| 标准包装： | 260 |
| 功能： | 控制器 |
| RF 型： | 通用 |
| 次要属性： | I²C 接口 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
| 其它名称： | 1016-1473 XR18W750IL48-F-ND |
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XR18W750
REV. 1.0.0
WIRELESS UART CONTROLLER
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
? Logic 0 = Force DTR# output HIGH (default).
? Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
? Logic 0 = Force RTS# HIGH (default).
? Logic 1 = Force RTS# LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the enhanced UART. But it is available for use during Internal
Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must be set to
logic 0 .
? Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
? Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
? Logic 0 = Disable loopback mode (default).
MCR[7:5]: Reserved
For normal operation, these register bits should be ’0’.
5.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
? Logic 0 = No data in receive holding register or FIFO (default).
? Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
? Logic 0 = No overrun error (default).
? Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
? Logic 0 = No parity error (default).
? Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
? Logic 0 = No framing error (default).
? Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
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相关代理商/技术参数 |
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| XR18W750IL48TR-F | 功能描述:UART 接口集成电路 XR18W750IL48TR-F RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR18W753 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER |
| XR18W753IL48 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHIP 868MHZ TO 956MHZ RF TRANSCEIVER |
| XR18W753IL48-F | 功能描述:射频接收器 UART RoHS:否 制造商:Skyworks Solutions, Inc. 类型:GPS Receiver 封装 / 箱体:QFN-24 工作频率:4.092 MHz 工作电源电压:3.3 V 封装:Reel |
| XR18W753L48-0A-EB | 功能描述:界面开发工具 900MHz RF EVAL Board RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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