参数资料
型号: SCDV5542
元件分类: 显示用LED
英文描述: 5X5 DOT MATRIX DISPLAY, SUPER RED, 3.2 mm
封装: ROHS COMPLIANT, PLASTIC, DIP-14
文件页数: 4/16页
文件大小: 675K
代理商: SCDV5542
SCDV5540, SCDV5541, SCDV5542, SCDV5543, SCDV5544
2006-01-23
12
Microprocessor Interface
The microprocessor interface is through the serial port, SPI port or
one out of eight data bits on the eight bit parallel port and also con-
trol lines SDCLK and LOAD.
Power Up Sequence
Upon power up display will come on at random. Thus the display
should be reset at power-up. The reset will set the Address Regis-
ter to Digit 0, User RAM is set to 0 (display blank) the Control Word
is set to 0 (100% brightness with Lamp Test off) and the internal
counters are reset.
Cascading Multiple Displays
Multiple displays can be cascaded using the CLKSEL and CLK I/O
pins as shown below. The display designated as the Master Clock
source should have its CLKSEL pin tied high and the slaves should
have their CLKSEL pins tied low. All CLK I/O pins should be tied
together. One display CLK I/O can drive 15 slave CLK I/Os. Use
RST to synchronize all display counters.
SCDV554X Interface with Motorola 68HC05C4 Microprocessor (using SPI port)
Cascading Multiple Displays
IDCD5232
OSC1
PA0
38
11
39
OSC2
RST
1
68HC05C4
U1
SDCLK
RST
LD
GND
CS
CLK I/O
CC
V
DATA
CC
V
40
ID
+
0.01 F
TAN
22 F
CC
V
VCC
PA2
9
20
PA1
10
SCLK
33
MOSI
32
1
2
6
7
13
12
9
8
14
GND
CC
V
11
CC
V
10
IDCD5030
RST
CLK SEL
Intelligent Display
CC
V
DATA
SDCLK
LOAD
14 more displays
in between
DATA
SDCLK
Decoder
Address
Address Decode 1-14
A0
A1
A3
RST
CLK I/O
Intelligent Display
DATA
RST
SDCLK
CLK I/O
LOAD
CLK SEL
Chip
0
15
A2
LD
CE
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